The present invention relates generally to multistage amplifier circuits, and in particular, to a technique for tuning an inter-stage matching network included in a multistage amplifier.
Network matching is an important part of radio frequency (RF) circuit design. With multistage RF amplifiers, i.e., amplification circuits having more than one amplifier cascaded together, it is typically necessary to provide both input matching networks and output matching networks, as well as inter-stage matching networks between the amplifiers included in the multistage circuit.
Input and output matching of a multistage RF amplifier can be generally done using conventional source-pull and load-pull techniques. In many cases, input and output matching can be readily accomplished using off-circuit (i.e., non-integrated) discrete components connected to a printed circuit board (PCB).
However, with multistage amplifiers implemented as single integrated circuits (ICs), the inter-stage matching can be difficult due to limited access to the inter-stage matching networks and manufacturing deviations in their component values.
A commonly used inter-stage matching network for integrated circuit RF power amplifiers consists of a high-pass inductor capacitor (LC) section, i.e., a series-connected capacitor and a shunt-connected inductor that is also used as a pull-up inductor connected to a direct current (DC) voltage supply for the circuit. The high-pass LC section is usually fabricated as part of the RF amplifier integrated circuit (IC). The values of components on the IC cannot be changed or are difficult to change once the IC is fabricated.
The performance of a fabricated inter-stage matching network may deviate from its simulated design because pre-fabrication simulation models of on-chip components in an IC are not always completely accurate. Furthermore, the simulation models of the on-chip RF components are often developed using small basic cells. This can cause discrepancies between simulated and measured results when many basic cells are put together to form a larger IC or component. These are common phenomen in RF circuit design, in general, and RF power amplifier design, in particular.
In an inter-stage matching network, small deviations of the inductance and capacitance values from desired values often result in mismatching. Such mismatching can significantly degrade the performance of a multistage amplifier. Specifically, the power-added efficiency (PAE), gain and output power of the multistage amplifier are dependant on the inductance and capacitance of the inter-stage matching network. Accordingly, the PAE, gain and output power can decrease significantly with minor deviations in the inductance and the capacitance of an inter-stage matching network.
There is thus a need for an improved method and apparatus for tuning an inter-stage matching network of an integrated multistage amplifier to boost amplifier performance.
In view of the foregoing, the present invention provides a circuit topology for tuning an inter-stage matching network included in an integrated multistage RF amplifier. An advantage of the invention is that it significantly improves the performance of multistage RF power amplifiers (PAs), particularly those used for wireless applications.
According to one embodiment of the invention, a tuning circuit includes one or more off-chip capacitors connected in shunt between ground and the voltage supply of a first stage of an integrated multistage amplifier. The capacitors can have values selected to effectively tune or compensate the inductance from a pull-up inductor included in an inter-stage matching network to provide improved inter-stage matching when inductance and capacitance values of the inter-stage matching network deviate from their desired values due to parasitics and/or when other components, such as input-stage and output-stage transistors of the amplifiers deviate from their pre-fabrication simulation models.
The foregoing and other features and advantages of the invention will become further apparent from the following detailed description of the presently preferred embodiments, read in conjunction with the accompanying drawings. The detailed description and drawings are merely illustrative of the invention rather than limiting, the scope of the invention being defined by the appended claims and equivalents thereof.